In VLSI design, the translation of the Register Transfer Level (RTL) to a netlist is typically done by complex VLSI-Synthesis software tools. When the RTL source is large, for example when complex System-On-Chip (SOC) integrated circuits are designed, synthesis becomes a long and tedious process. Therefore, if modifications to the RTL are introduced after synthesis is done, an Engineering Change Order (ECO) procedure is often preferred over a re-run of the synthesis tool. An example of ECO implementation techniques is given by Golson, in “The Human ECO Compiler,” Synopsys Users Group (SNUG), San Jose, 2004.